High performance flash memory devices, such as NOR-type flash memory devices, require high density and high operating speed as the device dimensions are scaled down. A low resistance Vss line, which connects source regions of flash memory cells situated between two word lines, is used to reduce memory core cell size, improve circuit density, and increase flash memory device performance.
In a conventional flash memory process flow, the Vss line can be formed by heavily doping the semiconductor substrate by using a Vss connection implant. In order to achieve a desirably low Vss resistance, a sufficient amount and a sufficient depth of doping are required along the Vss line in the semiconductor substrate. However, by introducing the amount and depth of doping required to sufficiently lower Vss resistance, a short channel effect known as drain induced barrier lowering (DIBL) can undesirably increase in a flash memory cell, such as a floating gate flash memory cell. By way of background, DIBL occurs when a voltage applied to the drain of the memory cell, such as a floating gate flash memory cell, causes the drain's electric field to directly affect the controllability of memory cell's channel. As a result of DIBL, the memory cell's threshold voltage decreases and leakage current increases, which detrimentally affect memory cell performance.
Thus, there is a need in the art for a floating gate flash memory cell, such as a NOR-type floating gate flash memory cell, having reduced DIBL and a sufficiently low Vss resistance.